Cypress Semiconductor /psoc63 /TCPWM0 /CNT[2] /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AUTO_RELOAD_CC)AUTO_RELOAD_CC 0 (AUTO_RELOAD_PERIOD)AUTO_RELOAD_PERIOD 0 (PWM_SYNC_KILL)PWM_SYNC_KILL 0 (PWM_STOP_ON_KILL)PWM_STOP_ON_KILL 0 (DIVBY1)GENERIC0 (COUNT_UP)UP_DOWN_MODE 0 (ONE_SHOT)ONE_SHOT 0 (X1)QUADRATURE_MODE 0 (TIMER)MODE

UP_DOWN_MODE=COUNT_UP, MODE=TIMER, QUADRATURE_MODE=X1, GENERIC=DIVBY1

Description

Counter control register

Fields

AUTO_RELOAD_CC

Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes. Timer mode: ‘0’: never switch. ‘1’: switch on a compare match event. PWM, PWM_DT, PWM_PR modes: '0: never switch. ‘1’: switch on a terminal count event with an actively pending switch event.

AUTO_RELOAD_PERIOD

Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes. ‘0’: never switch. ‘1’: switch on a terminal count event with and actively pending switch event.

PWM_SYNC_KILL

Specifies asynchronous/synchronous kill behavior: ‘1’: synchronous kill mode: the kill event disables the ‘dt_line_out’ and ‘dt_line_compl_out’ signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should be RISING_EDGE. ‘0’: asynchronous kill mode: the kill event only disables the ‘dt_line_out’ and ‘dt_line_compl_out’ signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.

This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is ‘0’.

PWM_STOP_ON_KILL

Specifies whether the counter stops on a kill events: ‘0’: kill event does NOT stop counter. ‘1’: kill event stops counter.

This field has a function in PWM, PWM_DT and PWM_PR modes only.

GENERIC

Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.

0 (DIVBY1): Divide by 1 (other-than-PWM_DT mode)

1 (DIVBY2): Divide by 2 (other-than-PWM_DT mode)

2 (DIVBY4): Divide by 4 (other-than-PWM_DT mode)

3 (DIVBY8): Divide by 8 (other-than-PWM_DT mode)

4 (DIVBY16): Divide by 16 (other-than-PWM_DT mode)

5 (DIVBY32): Divide by 32 (other-than-PWM_DT mode)

6 (DIVBY64): Divide by 64 (other-than-PWM_DT mode)

7 (DIVBY128): Divide by 128 (other-than-PWM_DT mode)

UP_DOWN_MODE

Determines counter direction.

0 (COUNT_UP): Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.

1 (COUNT_DOWN): Count down (to ‘0’). An underflow event is generated when the counter changes from a state in which COUNTER equals ‘0’. A terminal count event is generated when the counter changes from a state in which COUNTER equals ‘0’.

2 (COUNT_UPDN1): Count up (to PERIOD), then count down (to ‘0’). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals ‘0’. A terminal count event is generated when the counter changes from a state in which COUNTER equals ‘0’.

3 (COUNT_UPDN2): Count up (to PERIOD), then count down (to ‘0’). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals ‘0’. A terminal count event is generated when the counter changes from a state in which COUNTER equals ‘0’ AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).

ONE_SHOT

When ‘0’, counter runs continuous. When ‘1’, counter is turned off by hardware when a terminal count event is generated.

QUADRATURE_MODE

In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert ‘dt_line_out’ and ‘dt_line_compl_out’. Inversion is the last step in generation of ‘dt_line_out’ and ‘dt_line_compl_out’; i.e. a disabled output line ‘dt_line_out’ has the value QUADRATURE_MODE[0] and a disabled output line ‘dt_line_compl_out’ has the value QUADRATURE_MODE[1].

0 (X1): X1 encoding (QUAD mode)

1 (X2): X2 encoding (QUAD mode)

2 (X4): X4 encoding (QUAD mode)

MODE

Counter mode.

0 (TIMER): Timer mode

2 (CAPTURE): Capture mode

3 (QUAD): Quadrature encoding mode

4 (PWM): Pulse width modulation (PWM) mode

5 (PWM_DT): PWM with deadtime insertion mode

6 (PWM_PR): Pseudo random pulse width modulation

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